In on-chip and inter-chip data communication systems in which high data bandwidth is required, efficiently managing power dissipation and input/output (I/O) area is crucial. For instance, modern multi-core microprocessors typically have thousands of bits of on-chip data buses connecting processor cores and caches. Similarly, in high-performance servers, inter-chip connections (i.e., links) from processors to network switches or off-chip cache often require I/O buses hundreds of bits wide running at multiple gigabits per second (Gb/s) per-lane data rates. Compact and low-power I/O schemes are needed for these high-performance systems.
Among various circuit blocks in an I/O system, signaling power dissipated on a communication channel established with the I/O system consumes a significant portion of the overall I/O power. Since signaling power associated with a given signal is proportional to a square of the voltage swing of the signal transmitted on the channel, it is well known that reducing the signal swing will reduce the signaling power. However, low-swing signaling undesirably reduces the amplitude and signal-to-noise ratio of the signal received by a receiver, thereby creating a receiver sensitivity challenge. Realizing highly sensitive receivers running at multiple Gb/s data rates traditionally results in designs that are complex (and may even demand increased complexity in the transmitter design as well), with an adverse result of increased receiver and/or overall link power and associated area.
For example, U.S. Pat. No. 6,801,577 to Ranganathan et al. discloses a receiver based on a trans-impedance amplifier which transforms a received current signal into a corresponding voltage signal. However, this type of amplifier consumes considerable power to support high-speed signaling beyond a Gb/s data rate. Likewise, in a paper by Hui Zhang et al. entitled “Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 8, No. 3, pp. 264-272, June 2000, a detailed discussion is presented regarding low-swing on-chip interconnection schemes employing receivers that are either complex or consume significant power, making them poorly suited for applications requiring low power and/or compactness.